ACCELERATING FPGA VHDL VERIFICATION
Efficiency and quality is all a question of overview, readability, extensibility, maintainability and reuse, -and a good architecture is the answer. This applies for both Design and Verification.
This course contains a general introduction to modern verification methodology and to UVVM (Universal VHDL Verification Methodology) –the world-wide #1 VHDL-FPGA verification methodology, and alsothe fastest growing verification methodology independent of HDL.
On average half the development time for an FPGA is spent on verification. It is possible to significantly reduce this time, and major reductions can be accomplished with minor adjustments. In this course you will learn how to reduce development time and at the same time improve the quality.
The course will concentrate on FPGA verification and how a well structured testbench is constructed. Theory alternates with practical examples, as well as hands-on tutorials. It also covers important topics such as coverage, Bus Functional Models (BFM), debugging and randomization.
After the course, participants will know how to structure an FPGA verification platform, how to implement their testbenches, and how to write test sequencers, which can be understood by software and hardware developers. Participants will also learn how to use the complete VHDL-based UVVM verification platform within their own organization.
CONTENT I GOALS
Making a simple VHDL testbench step-by-step
Using procedures and making good BFMs
Applying logs, alerts, value and stability checkers, awaits, etc.
Making an advanced VHDL testbench step-by-step
Assertions, randomization, constrained random, coverage, debuggers, monitors
Verification components and testbench architecture for advanced verification
Making testbenches as simple as possible –adapting to the DUT complexity
Structuring, Debugging, Overview, Maintainability, Extendibility
Examples and labs using Universal VHDL Verification Methodology (UVVM)
THE TRAINER
Espen Tallaksen
is the CEO and founder of the newly established EmLogicand previously also Bitvis, both independent design centresfor embedded software and FPGA, with Bitvisas a leading Nordic company within its field and EmLogic soon to be. He graduated from the University of Glasgow (Scotland) in 1987 and has 30 years’ experience with FPGA and ASIC development from Philips Semiconductors in Switzerland and various companies in Norway. Duringtwenty years Espen has had a special interest for methodology cultivation and pragmatic efficiency and quality improvement.
One result of this interest is the UVVM verification platform that is the world-wide fastest growing FPGA verification methodology independent of HDL.
UVVM is already used by more than 1/3 of
all FPGA designers in Europe.
He is giving courses world-wide on how to design and verify FPGAs more efficiently and with a better quality
Requirements: Knowledge of VHDL, basic knowledge of verification I Duration: 5 days I Language: English I Price: 2.300,00 EUR net
More information
New Date!
24.02. - 28.02.2025 | 9 am – 1.30 pm | LIVE Online (instructor-led)
We are happy to offer further options such as live online sessions and on-site training upon request.
Où nous trouver
Cadlog S.A.S.
5 Rue de Copenhague
93290 Tremblay-en-France
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