ACCELERATING FPGA AND DIGITAL ASIC DESIGN
Digital design for FPGAs and ASICs has a huge improvement potential with respect to development time and product quality.
A lot of time is wasted on inefficient design and lack of awareness and knowledge of the most critical digital design issues. This also seriously affects the quality of the end product. The really goodthing is that this huge improvement potential can be realisedjust by making a few important changes to the way we design.
There will be a few examples on quite common bad approaches, and more examples on good approaches for architecture, Clock Domain Crossing (CDC), Coding, Reuse, etc.. Almost all examples are independent from both technology (FPGA/ASIC) and language (VHDL/Verilog /SystemVerilog).
The course is intended for FPGA designers and Digital ASIC designers, who wants to work smarter and more efficiently -and design products with higher quality.
CONTENT I GOALS
Structured FPGA development
Clocking and Timing Essentials, Part 1
Basic bus system consideration
Selected RTL coding details
Plug’n’Playreuse challenges
Design for Plug’n’Playreuse
HDL flexibility and risks
Clocking and Timing Essentials, Part 2
Verification Essentials
Design structure and Design for modified reuse
Design corner cases
Coding issues
Developing an FPGA module -with a strong focus on efficiency, quality and modifiability
Quality Assurance - at the right level
THE TRAINER
Espen Tallaksen
is the CEO and founder of the newly established EmLogicand previously also Bitvis, both independent design centresfor embedded software and FPGA, with Bitvisas a leading Nordic company within its field and EmLogic soon to be. He graduated from the University of Glasgow (Scotland) in 1987 and has 30 years’ experience with FPGA and ASIC development from Philips Semiconductors in Switzerland and various companies in Norway. Duringtwenty years Espen has had a special interest for methodology cultivation and pragmatic efficiency and quality improvement.
One result of this interest is the UVVM verification platform that is the world-wide fastest growing FPGA verification methodology independent of HDL.
He is giving courses world-wide on how to design and verify FPGAs more efficiently and with a better quality
Requirements: Knowledge of FPGA Design or Digital ASIC Design I Duration: 2 days I Language: English I Price: 1.500,00 EUR net
More information
Dates
20.01. - 23.01.2025 | 9 am – 1 pm | LIVE Online (instructor-led)
We are happy to offer further options such as live online sessions and on-site training upon request.
Où nous trouver
Cadlog S.A.S.
5 Rue de Copenhague
93290 Tremblay-en-France
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