Questa CDC
The industry’s most comprehensive and easy-to-use clock-domain crossing verification solution
Questa CDC by Siemens identifies errors using structural analysis to recognize clock domains, synchronizers, and low power structures via the Unified Power Format (UPF).
Questa CDC Verification generates assertions for protocol verification along with metastability models for reconvergence verification.
Why choose Questa CDC?
High Performance Analysis
Using only your RTL (and UPF power intent file), Questa CDC solutions automatically generate and analyze assertions to rapidly identify chip-killing clock-domain crossing (CDC) issues.
Automated Assertion Generation & Analysis
Using only your RTL and UPF power intent file, Questa CDC solutions automatically generate and analyze assertions to rapidly identify chip-killing clock-domain crossing (CDC) issues.
Industry-Leading Scalability and QoR
When analyzing billion-gate designs, minimizing “noise” is critical. Questa CDC comprehensive, hierarchical, formal-based analysis searches through DUT elements for high throughput and noise minimization, simultaneously providing industry-leading scalability and high quality of results while enabling CDC IP reuse.
Ease of Set-Up and Use
Questa CDC supports the Synthesis Design Constraints (SDC) format for clock- and port- domain settings, and it includes a TCL scripting environment with powerful control and reporting capabilities. Questa CDC automatically identifies your clocks and clock distribution strategy, minimizing set-up time.
White Paper
In this paper, we present an algorithm to handle CDC violations as part of the objective function for sequential clock gating optimizations. With the proposed algorithm, we have obtained an average of 22% sequential power savings – this is within 3% of the power savings obtained by the CDC unaware sequential clock gating. In comparison, the state-of-the-art twopass solution is leading to an almost complete loss of power savings.
When Good Clocks Go Bad
Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. An RTL or gate-level simulation of a design that has multiple clock domains does not accurately capture the timing related to the transfer of data between clock domains. As a consequence, the simulation does not accurately predict silicon behavior, and critical bugs may escape the verification process.
Using only your RTL (and UPF power intent file), Questa CDC solutions automatically generate and analyze assertions to rapidly identify chip-killing clock domain crossing (CDC) issues. Results can also be transmitted to the master verification progress database via UCDB. No knowledge of formal or property specification languages is required.
The Solution: Questa CDC Verification
Questa CDC Solutions identify errors that have to do with clock domain crossings – signals (or groups of signals) that are generated in one clock domain and consumed in another. It does so with structural analysis and recognition of clock domains, synchronizers, and low power structures (via UPF); and with generation of metastability models for reconvergence verification. The technology checks all potential failure modes and presents to the user familiar schematic and waveform displays. Additionally, in concert with simulation, this technology can be used to inject metastability into the functional simulation to verify the DUT correctly processes asynchronous
clocks.
White Paper
Siemens verification solutions for FPGA provide a complete set of tools that work across all FPGA families and development platforms. This presentation discusses UVM, Formal, Design Solutions, QVIP, Visualizer, and Verification Run Manager.
Products for FPGA Design and Verification
Questa AutoCheck
Questa AutoCheckest une application automatisée vous aidant à trouver les bogues dus à des erreurs de codage RTL courantes dès le début de votre conception.
Questa CDC
Questa CDC de Siemens utilise l'analyse structurelle pour reconnaître les clock domains, les synchroniseurs et les structures à faible consommation.
HDL Designer
HDL Designer offre un environnement de conception HDL complet, garantissant un flux de conception FPGA/ASIC structuré.
Questa Advanced Simulator
Questa Advanced Simulator est un simulateur et une machine de débogage qui réduit le risque de validation de vos conceptions FPGA et SoC complexes.
Questa Verification IP
Questa Verification IP aide les ingénieurs à se concentrer sur les aspects essentiels des conceptions, et éviter les BFM, composants de vérification ou VIP
Vérification de la conception FPGA avec Questa Prime
La solution Questa est un assemblage de technologies, de méthodologies et de bibliothèques pour la vérification de la conception FPGA et ASIC moderne.
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